Development of 2.4 GHz RF transceiver front-end chipset in 0.25 /spl mu/m CMOS

This paper presents the design of a 2.4 GHz RF transceiver front-end chipset in 0.25 /spl mu/m CMOS technology. The designed chipset includes a fully monolithic receiver front end consisting of LNA, mixer and two variations of power amplifiers (PA), one for high output power and efficiency, and the other for good linearity. The integrated receiver provides simulated voltage gain of 22.7 dB, NF of 6.6 dB, IIP3 of -15.5 dBm, and consumes 21 mW power from a 1.5 volt power supply. The high-efficiency versions utilize class F/inverse class F matching to achieve power added efficiency (PAE) of over 50% with an output power of up to 350 mW. The linear PA utilizes differential class B push pull architecture and provides an IM3 less than -35 dB with a 22.5 dBm output power and power added efficiency (PAE) of 20%. The circuits are under fabrication in National Semiconductor's 0.25 /spl mu/m CMOS facility and the measurement results will be presented in the final version.