Low power implementation of FFT/IFFT processor for IEEE 802.11a wireless LAN transceiver

In an orthogonal frequency division multiplexing (OFDM) system, the fast Fourier transform (FFT) is one of the major processing blocks. The inverse FFT (IFFT) is used to modulate a serially transmitted signal into parallel orthogonal signals while demodulation is achieved by FFT at the receiver. With the limited battery life, energy efficiency is becoming crucial in the design of next generation wireless systems. Typically, power conservation is used in the hardware design of such systems. This paper presents an efficient scheme using reduced precision and wordlength optimization to reduce power and increase performance of FFT in the transmitter for IEEE 802.11a WLAN applications. With reduced input bits during transmission, simulation results show that the power consumption of the butterfly functional unit can be reduced considerably.