Early probabilistic noise estimation for capacitively coupled interconnects

One of the critical challenges in today's high-performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools are effective at analyzing and identifying noise in the postroute design stage when detailed parasitic information is available. However, noise problems identified at this stage of the design cycle are very difficult to correct due to the limited flexibility in design and may cause additional iterations of routing and placement which adds costly delays in its time to market. In this paper, we introduce a probabilistic preroute noise analysis approach to identify postroute noise failures before the actual detailed route is completed. We introduce new methods to estimate the RC characteristics of victim and aggressor lines, their coupling capacitances, and the aggressor transition times before routing is performed. The approach is based on congestion information obtained from a global router. Since the exact location and relative position of wires in the design are not yet available, we propose a novel probabilistic method for capacitance extraction. We present results on two high-performance microprocessors in 0.18 /spl mu/m technology that demonstrate the effectiveness of the proposed approach.