An embedded built-in-self-test approach for analog-to-digital converters

In this paper. an embedded built-in-self-test approach for analog-to-digital converters (ADCs) is presented. This architecture can test the parameters of ADC. which includes the differential nonlinearity (DNL) error, integral nonlinearity (INL) error, offset error (V/sub OSE/), gain error (V/sub GE/), and sampling rate. The proposed circuit is designed and simulated with an 8-bit ADC by using a CMOS 0.35 /spl mu/m 1P4M process. The accuracy of DNL test, INL test, VOSE test, and VGE test depend on the testing time. For the case of 256/spl mu/s, the accuracy can achieve 1/10LSB. and longer testing time results in higher accuracy.