A new VLSI design for Viterbi decoder based on ASIP

Trellis Code Modulation (TCM) has been widely used because it can obtain 2.55/spl sim/7.37 dB coding gain without bandwidth expansion or reduction of the effective information rates. Since Viterbi decoder plays an important role in the realization of HDTV system, we conduct the research and development on integration of Viterbi decoder. This paper proposes a new VLSI design of Viterbi decoder using ASIPs based on hardware/software co-design idea. It reduces the total design time and enhances the reliability of VLSI. We have successfully used this method for the design of Viterbi decoder in the ASTC-HDTV receiver chip.