Realization of a monochip Viterbi decoder in ASIC technology

An ASIC realization of a Viterbi decoder is presented for the convolutional code of rate 1/2 and constraint length 7 (generator polynomials 133 and 171) and the code derived from it by puncturing to provide a code of rate 3/4, or by reuse of the same polynomials to get codes of rate 1/4 and 1/8. The technology is CMOS 1.5 mu m, and the chip size is 14*14 mm/sup 2/. It contains about 45000 gates plus 3 three-port RAMs. The maximum user data rate of the chip in industrial worst-case conditions at 17 Mbit/s. The circuit is comprised of a coder and a decoder whose characteristics are described.<
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