A parameterized VLSI video-rate histogram processor

A real-time video rate histogram processor has been designed, fabricated and tested. A pipelined architecture was chosen to support 10 MHz sample rates. The architecture was then implemented using high-level CAD tools to automate the design. Finally, the fabricated processor was connected to a second chip which implements a programmable look-up table function, to demonstrate real-time histogram equalization of 10 MHz video data.