Optimization and control of V/sub DD/ and V/sub TH/ for low-power, high-speed CMOS design

It is essential to control supply voltage V/sub DD/ and threshold voltage V/sub TH/ for low power, high-speed CMOS design. In this paper, it is shown that these two parameters can be controlled by designers as objectives of design optimization to find better trade-offs between power and speed. Quantitative analysis of trade-offs between power and speed is presented. Some of the popular circuit techniques and design examples to control V/sub DD/ and V/sub TH/ are introduced. A simple theory to compute optimum multiple V/sub DD/ and V/sub TH/ values is described. Scaling scenarios of variable and/or multiple V/sub DD/ and V/sub TH/ values is discussed to show future technology directions.