Performance evaluation of the communications protocol processor

The performance evaluation of the protocol processing elements of a multimedia communications processor, is described. Specialized frame and header processing units were simulated using a high-level hardware model to produce typical path lengths for known protocols. A performance evaluation based on extrapolated data was performed to evaluate variable traffic and application conditions. The results indicate that such an architecture can allow handling of data for 5-10-Mb/s links without modification of existing protocols. The variation would depend on the number of layers supported.<
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