Parallel and cascade microprocessor implementations for digital signal processing

Microprocessors have achieved great popularity because they are inexpensive, convenient, and flexible. A microprocessor with an architecture chosen to efficiently perform digital signal processing algorithms would retain these advantages when used to implement digital signal processing. One such architecture is the Research Signal Processor (RSP), which was designed by A. Peled to gain these advantages. In order for such a microprocessor to be a cost effective signal processing solution, however, it is necessary that it be capable of implementing a wide range of digital signal processing applications, so that the cost of developing an economical LSI version can be borne by many applications. In addition to efficiently implementing single microprocessor applications, then, it is also important to have the capability of connecting into systems that can efficiently implement large applications. In this paper, it is demonstrated that many digital signal processing tasks can be decomposed into subtasks that permit simple parallel and cascade multiple microprocessor implementations. In some cases, several implementations of the same and competing algorithms will be presented and contrasted. The I/O functions required to support these structures are discussed, and the RSP I/O capability which was chosen to meet these requirements is described. The effect of the microprocessor I/O capability on the total system cost will also be discussed.