The systolic phase rotation FFT-a new algorithm and parallel processor architecture

A new FFT algorithm and its implementation in a VLSI-based parallel processor are described. The innovation provided by the new algorithm is the high degree of localization of data shuffle storage locations between successive computational stages in a pipeline or recursive FFT. This allows the simultaneous transformation of R* log/sub R/(N) data channels in a recursive N-point FFT processor, where R is the radix of the transform. The pipeline processor has a constant geometry architecture. The throughput rate achievable with this pipeline architecture is R times the required processor and memory access rates. The new architecture eliminates the delay commutator switches which characterize the Purdy McClellan processor and replaces them with distributed random access memories and phase rotations at each stage to perform the data shuffling.<
>