A hierarchical block-based modeling methodology for SoC in GENESYS

System-on-a-chip (SoC) designs promise to play a dominant role in the future of gigascale integrated (GSI) systems. Existing chip modeling tools based on technology parameters for projecting physical performance are ill suited for projecting the performance of SoC designs. A new modeling methodology for heterogeneous SoCs has been developed for a technology based simulation tool (GENESYS). The hierarchical block modeling methodology mimics the structure of a SoC design by partitioning the chip into blocks as is typical of megacell based design methodologies. The new model allows for exploration of the impact of technology choices on SoC performance for a wide variety of designs. An example SoC is simulated showing improved accuracy of the heterogeneous compared to the homogeneous model. A percentage error of 18.6% for the die size calculation in the homogeneous model is reduced to 3% with the heterogeneous modeling. In addition, the scaling characteristics of the example SoC are shown for the ITRS technology generations. Results show that the same design implemented in 35 nm technology could achieve a factor of 6 increase in clock frequency while operating at less than 1 W on a 5 mm/sup 2/ die.