An 8-bit 200 MS/s CMOS folding/interpolating ADC with a reduced number of preamplifiers using an averaging technique

An 8-bit 200 MSample/s CMOS folding/interpolating ADC chip was implemented by using a 0.35-/spl mu/m double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array in comparison with the published folding/interpolating ADC chips. The delay time of digital encoder block was reduced to 1.3 ns from 2.2 ns by using a DCVSPG-style differential logic. The chip area and the measured power consumption were 1.02 mm/sup 2/ and 120 mW respectively at the supply voltage of 3.3 V.