Implementation of a new MPEG-2 transport stream processor for digital television broadcasting

We introduce a real-time, dual independent output MPEG-2 transport stream (TS) processor designed specific for the China HDTV testing zones. The processor is a single piece of equipment, of which the core functions are realized in FPGA and DSP. Key technologies include a program clock reference (PCR) correction and a packets controller, which are important for TS processing, are described in detail. An improved PCR correction scheme developed by the authors is also proposed.