Macro-testability and the VSP

The authors describe a design-for-testability scheme and test generation for a digital video signal processing IC. The video signal processor (VSP) IC has an advanced multiprocessor architecture and is capable of executing 1400 MOPS (million operations per second) at an operating frequency of 27 MHz. The testability scheme developed makes full use of the macro-test concept. Several new methods for enhancing the macro-test concept are described. The testability scheme is shown to be efficient in terms of test costs and area overhead and is also scalable to the next generation of VSP ICs.<
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