Parametric yield estimation for deep sub-micron VLSI circuits

Summary form only given. Experimental silicon production facilities currently approach the region of circuits exhibiting 70 and 50 nanometer feature sizes. These will enter the market in a few years. By that time the industrial design environments have to be ready to serve the needs of such technologies. Experiments performed in new fabrication facilities indicate that there will be a new challenge: the control of the statistical variations of layout dimensions and material parameters due to imperfect processing. Some experiments indicate that such variations may lead to fluctuations of the speed of circuits of about 14% within one die. This fosters the conclusion that those statistical variations must enter the design flow. First of all the statistical features of device and layout parameters have to adequately characterized by appropriate mathematical models on the basis of advanced metrology. Secondly the libraries of logic components have to be updated to capture the statistical device features. Thirdly the simulation engines have to be prepared to produce not only nominal (and possibly worst case) data but also statistical performance distributions and densities.