Two hardware implementations for the Montgomery modular multiplication: sequential versus parallel

Modular multiplication is the most dominant part of the computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. This paper describes the characteristics of two architectures designed to implement modular multiplication using the fast Montgomery algorithm: the first FPGA prototype has an iterative sequential architecture while the second has a systolic array-based architecture. The paper compares both prototypes using the time/spl times/area classic factor.