Design and Development of a 68-Lead Nonhermetic Leaded Chip Carrier

The design and development of a 68-lead nonhermetic leaded chip carrier (CC) suitable for Packaging a high-speed bipolar gate array device with several watts of power dissipation are covered. This CC was designed to make use of thin-film hybrid assembly technology with a package outline generally consistent with the JEDEC Leaded Type A Standards. The CC is compatable with different silicon integrated circuit (SIC) attachment methods and provides high thermal performance. The CC was constructed using titanium/palladium/gold thin-film circuitry on 99.5 percent alumina, with package leads attached to the thin-film circuit by thermal compression bonding. The assembly of the silicon device to the ceramic involved epoxy die bonding and thermosonic gold wire bonding. The majority of the work on the CC was performed with a thermal test chip. The assembled CC device was coated with RTV and an epoxy for environmental protection, and the external leads were formed around a plastic insert to meet the JEDEC outline. An aluminum heat spreader was attached to the back surface of the ceramic. A surface solder method for the attachment of the CC to a printed wiring board (PWB) was developed. The fatigue resistance of the solder joints was demonstrated to be adequate. Temperature rise versus power measurements were made on CC's with and without heat spreaders and on a CC/PWB assembly. From the data, the thermal · resistances of the packages were determined and used in defining a simple model of the CC package and a CC/PWB package combination. Depending on the environment of the CC device, a forced air velocity range was determined to maintain chip junction temperatures below allowed maximums. It was determined that the thermal performance of the CC packaged device would be satisfactory for use with a 2-W chip in a moderate forced air environment.