A Coaxial Interconnection System for High Speed Digital Processors

The cost of interconnecting integrated circuits in large arrays has always been a considerable factor in establishing the operating cost effectiveness of high speed digital processors. Now, with the introduction and increasing use of ICs operating at subnanosecond speeds, interconnection systems have become even more of an economic factor because of the electrical limitations they can impose on the maximum speeds at which information can be processed. The electrical effects exerting the greatest influence are propagation velocities, internal crosstalk, sensitivity to RFI and the need for impedance matching between devices. While there are additional mechanical problems in miniaturization, heat dissipation and production costs, the electrical problems have provicled a sufficient incentive to undertake the development of a more compatible interconnecting system. The resulting new system is a discretionary wired, fully shielded and coaxial interconnection system. It has been primarily designed for use with logic elements having pulse rise times in the subnanosecond range, and in its present form is capable of handling pulse rise times of less than 100 picoseconds. A typical system employs conductors with a characteristic impedance of 50 ohms and is capable of .050" center connections. The primary interconnections are made with .010" O.D. 50 ohm TFE insulated coaxial conductors that are formed "in-situ" by the manufacturing process. The system is fully compatible with printed circuit techniques and additional "non-critical" circuitry may be added to the system by these means. The system can also be made compatible with multilayer technology, and "Hybrid" systems may be produced. Although the system has many unique features, it is constructed with state-of-the-art materials and processes. It is capable of manufacture, in-process and final inspection by numerically controlled automatic machines. In the basic systern all interconnections are made by a mass process on an exposed surface of the assembly. Since these connections are exposed, changes, while they must be made manual y, can be accommodated. The reliability of the system has not been estab ished but its simplicity, coupled with the fact that it generated no more connections than those of the original circuit diagrams, leads us to believe that it will be very good. It has been established that this new interconnection system can provide predefined and easily controlled characteristics of impedance, minimum attenuation and delay with the precision necessary for constructing high speed processors. In SO doing it can either eliminate or substantially reduce other problems of an electrical nature and offers a maximum of design flexibility with a minimum of engineering and its accompanying costs.