Power Optimization of GaAs Implanted FET's Based on Large-Signal Modeling

Large-signal models for ion-implanted, MMIC-compatible GaAs FET's are reported using different techniques. There are (i) S-parmneter meawrements, (ii) low-frequency capacitances combined with dc Z-V characteristics, and (iii) physical data. The results obtained with each model are compared to high-frequency power measurements, and the relative merits of each technique are discussed. The models permit investigation of the influence of frequency, implantation energy, doping density, drain bias, recess depth and gate length on the small- and Iarge-signal FET parameter and saturation mechanisms. FET's fabricated with these data give optimum gain and power characteristics at the desired frequency of operation.