Synchronous logic synthesis: circuit specifications and optimization algorithms

Synchronous logic networks are characterized in terms of graphs, logic functions, and synchronous don't care conditions induced by the external and internal interconnection of the network. Algorithms to compute the don't care set for each local logic network. Algorithms to compute the don't care set for each logic function of the network from the synchronous don't care conditions that characterize the entire network are presented. Such local don't care conditions can be used to optimize locally each logic function to produce a smaller, faster, and better testable network.<
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