Mapping systolic FIR filter banks onto fixed-size linear processor arrays

A technique for mapping systolic finite impulse response (FIR) filter banks onto fixed-size processor arrays is presented. It is based on the time-sharing properties of c-slow circuits. The technique can be further developed to a formalism and holds high potential for automatic realization. It has been applied to the mapping of systolic filter banks onto a fixed-size array of transputers.<
>