A process and geometry driven device macro model for statistical simulation of bipolar ICs

A method of modeling bipolar semiconductor devices for circuit simulation is presented. Device layout geometric differences are accurately included in circuit simulation models without requiring a separate model for each layout geometry. To ensure that the simulated results closely match the measured performance, all parasitic junctions and capacitances are modeled in detail by utilizing subcircuit macros. Functional model parameters allow statistical circuit simulation from uncorrelated process parameters.<
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