1.25 GHz 26-bit pipelined digital accumulator

The authors described the design and implementation of a 1.25-GHz 26-bit pipelined accumulator. The chip was implemented using capacitor diode-coupled FET logic (CDFL), employing the planar GaAs depletion mode process. Performance equivalent to that of a fully custom design was achieved with a standard cell design approach. Fully functional chips have been fabricated and operated at 1.25 GHz with 2.6 W total power dissipation. The accumulator chip is 4.6 mm*3.9 mm and contains approximately 2000 equivalent logic gates. It is concluded that this device is suited for use in direct digital synthesis (DDS) and signal-processing applications. In particular, the results obtained demonstrate that DDS systems of up to 500-MHz bandwidths are possible.<
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