Novel GaAs FET modeling technique for MMICs

A novel procedure has been developed to extract an accurate and consistent small-signal equivalent circuit of an FET from the measured S-parameters. The parasitic circuit elements are pre-extracted from three to five sets of zero drain-to-source bias S-parameters measured at the desired gate-to-source and drain-to-source biases. In the second step, the S-parameters are fitted to the equivalent circuit of an FET in the common-source, common-drain, and common-gate configurations to improve the accuracy and consistency of the modeling. An excellent agreement between modeled and measured S-parameters, stability factor, and maximum stable (available) gain was obtained.<
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