A 4 ns BiCMOS translation-lookaside buffer

A 64-entry, fully associative translation lookaside buffer (TLB) which has pin-to-pin address translation time of 3.6 ns is described. This translation speed is achieved with a BiCMOS content addressable memory (CAM) and static-random-access-memory (SRAM) arrays that maintain small signal swings throughout the critical translation path.. The TLB has been integrated as a stand-alone chip in a 0.8- mu m BiCMOS technology. The circuit operates from a 5.2-V supply with emitter-coupled-logic (ECL) compatible input and output levels. The power dissipation, excluding the power dissipated in the physical address output buffers, is less than 600 mW.<
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