A 55 ns 4 Mb EPROM with 1-second programming time

A 55-ns, 4-Mb (256-kW*16 b) EPROM with a 1-s programming time is described. By use of 0.8- mu m lithography, a memory cell size of 2.8*2.8 mu m/sup 2/ is achieved, resulting in an 8.13*9.27 mm-die. A polycide structure is used to decrease the word line resistance and interconnection resistance, and a lightly doped drain (LDD) structure is used in the peripheral gates of pMOS and nMOS transistors to prevent degradation of characteristics induced by hot carriers. A double-well structure is adopted to improve the characteristics of short-channel pMOS transistors by optimizing the concentration of well regions. The process parameters for this device are summarized. To decrease the word line resistance, the memory array is divided into four planes, with one X-decoder for each pair of planes. This results in a 25% improvement in the access time, with a 10% die size penalty.<
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