A study of stress-induced p/sup +//n salicided junction leakage failure and optimized process conditions for sub-0.15-/spl mu/m CMOS technology

We have clarified that mechanical stress combined with a shallower junction at the active edge is the main cause of junction leakage current failure of shallow p/sup +//n salicided junctions for sub-0.15-/spl mu/m CMOS technology, especially those with narrow active width. Mechanical stress results in the penetration of a Self-Aligned siLICIDE (SALICIDE) layer at the corner region of the narrow active line. Moreover, a novel electrochemical etching with TEM shows shallower junctions at the active edge due to the bending up of the junction profile. We found that the application of a shallow trench isolation (STI), top corner rounding (TCR) process suppresses the mechanical stress of STI's top corner and thus eliminates the stress-induced p/sup +//n salicided junction leakage failure. Furthermore, we optimized the Co SALICIDE process using a Ge/sup +/ pre-amorphization in a narrow p+/n salicided junction.