Stability Analysis of an Nth Power Digital Phase-Locked Loop - Part II: Second- and Third-Order DPLL's

The behavior of a digital phase-locked loop (DPLL) which tracks the positive-going zero crossings of the incoming signal can be characterized by a nonlinear difference equation in the phaseerror process. This equation was first presented by Gill and Gupta for the CW loop, and modified by Osborne and Lindsey for the
N
th power loop. Some stability results had been previously obtained by other authors for first- and second-order loops by linearizing the equation about the steady-state solution. In Part I, a mathematically more rigorous and powerful approach was introduced whereby the acquisition behavior was studied by formulating the equation as a fixedpoint problem. Stability results can be obtained by using theorems such as Ostrowski's Theorem and the Contraction Mapping Theorem. Part I then presented some new stability results (and rederived some previously obtained results) for first-order DPLL's. In Part II, we present the results for the second- and third-order DPLL's. It is shown how both second- and third-order DPLL's have gain-dependent limitations on the frequency offsets which can be withstood. These restrictions imply that the higher order DPLL's cannot track a frequency ramp, regardless of the ramp slope, and are in contrast to the results for analog loops. Important restrictions on the signal power are also noted for both loops.