A Single-Chip I2L PCM Codec

A single-chip CPCM codec is described. This chip, which is fabricated in bipolar technology, meets all the
D3
specifications. The circuit is capable of operating in a fully asynchronous transmit and receive mode, and provisions are made, for zero-code suppression and
A/B
signaling. Even with this signaling, the codec achieves a worst case idle-channel noise of 13 dBrn
C
0.