A 40-nm 131-mW 6.4-Gb/s 256 × 32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems

High-mobility communication technology enables important applications in the near future. In such scenarios, the wireless channel exhibits high Doppler spread, which makes orthogonal frequency division multiplexing (OFDM) adopted in current wireless system suffer from severe inter-carrier interference (ICI). The orthogonal time frequency space (OTFS) technique is a promising modulation to address this issue. It demonstrates higher resilience to Doppler spread than OFDM in terms of bit error rate (BER) at the expense of higher detection complexity. This work presents the first high-throughput multi-user multi-input multi-output (MU-MIMO) detector for OTFS communication systems. A low-complexity message-passing (MP) detection algorithm is proposed to achieve 93% lower computational complexity by leveraging the structure of Gram matrix. A memory-efficient residual noise (RN) update scheme is devised to reduce the memory size for storing the partial interference by 94%. The proposed MP detector achieves a 60% reduction in latency by employing mean computation unit (MCU) and dual-mode multiplier. In addition, a 91% memory access reduction and an 89% memory size reduction in the channel memory bank are achieved, respectively, by leveraging layer ordering, partial Gram matrix saving, and block diagonal approximation. The chip supports up to 32 users, 256 receive antennas, and 256-QAM modulation. Fabricated in a 40-nm CMOS technology, the chip integrates 6.76 M gates in area of 6.47 mm2 and it delivers a maximal throughput of 6.4 Gb/s. The power consumption is 131 mW at 200 MHz from a 0.9 V supply. In comparison to state-of-the-art MU-MIMO OFDM detectors, this work achieves 3.3-to- $21.3{\times }$ higher maximal throughput and 2.2-to- $67.0{\times }$ lower normalized energy, in addition to higher resilience to Doppler spread.