An embedded 0.8 V/480 /spl mu/W 6b/22 MHz flash ADC in 0.13-/spl mu/m digital CMOS process using a nonlinear double interpolation technique

For high-data-rate wireless communication, low-voltage baseband converters integrated with DSP in deep submicrometer processes are area- and power-efficient. Through careful architecture selections and circuit techniques, this paper demonstrates a low-voltage (0.8 V), low-power (480 /spl mu/W), 6-b/22-MHz flash-interpolation ADC which occupies 0.3 mm/sup 2/ and achieves 33 dB SNDR and 47 dB SFDR. The power efficiency of this converter is 0.6 pJ/conv-step which compares favorably with all published results. We also introduce a nonlinear double interpolation technique that enables the use of a 0.13-/spl mu/m standard digital CMOS process without special resistors.