Design of a logic circuit for microprocessor recovery from a power failure and a transient fault

Nonredundant microprocessor
({\mu}p)
controlled systems often necessitate the use of built-in algorithms and/or hardware logic in order to ensure reliable and smooth functioning of the
{\mu}p
whenever a fault occurs during normal operation or power-up sequence. In this paper, we present a class of fault-detection algorithms and hardware recovery circuit along with their implementation methodology. The novelty of the proposed design lies in the simplicity of the logic circuit and software algorithms and their ready adaptability to any
{\mu}p
.