A design of CMOS polycell for LSI circuits

We have designed CMOS polycells with a uniform height for LSI random logic circuits. The design objective was to minimize the product of propagation delay and chip area while allowing noise margins to be at least 25 percent of
V_{dd}
. Designable parameters were identified to be channel widths in
p
-type and
n
-type transistors. Analytical models were derived to show the existence of an optimal solution point. Physical interpretations of models were also given. SPICE was used to simulate propagation delays and noise margins in inverter (INR), 2- and 3-input NAND and NOR gates under worst-case conditions. The chip performance of polycell-based CMOS circuits was then estimated by averaging performances of these five logic gates. With
3.5-{\mu}m
design rules, the channel widths in
p
-channel and
n
-channel transistors were designed to be
35{\mu}m
and
17{\mu}m
, respectively.