An improved successive-approximation register design for use in A/D converters

An improved design for a successive-approximation register (SAR) for use in A/D converters is presented. Thne proposed design is suitable for
I^{2}L
implementation such that a definite savings in devices is obtained over previous designs using the separate sequencer and code register approach. This particular design scheme operates in a fully synchronous mode with the clock allowing a reduction in propagation delay to be realized.