A methodology for debugging ASIC prototypes in the field

A step-by-step methodology for debugging and solving wafer sort and final-test prototype failures in application-specific integrated circuits (ASICs) is provided. The uses of schmoo plots, datalogs, and fault analysis are described, and a checklist for investigating problems is given. Most of the work can take place at the remote site, using simulators, schematics, and standard information provided by the test engineer.<
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