ParCha: A New Resource-Efficient TDC With Salient Linearity Performance Using Parallel Short Chains

Time-to-digital converters (TDCs) is a widely used high-precision time interval measurement unit. However, the field programmable gate array (FPGA)-based TDC is known to suffer from the nonlinearity problem and is vulnerable to temperature variations. To tackle this issue, conventional approaches often entail excessive redundant resources or cumbersome calibration efforts. In light of this, a new resource-efficient TDC using parallel short chains (ParCha) is proposed in this article. ParCha is a variant of low dead time tapped delay line (TDL) TDC but in this TDC, the long delay chain is “folded” into several short parallel pieces. The key insight here is to reallocate the measurement range of each short piece by introducing an appropriate fix delay so that they can equivalently formulate a long chain. This can effectively mitigate the clock skew problem and minimize delay cell heterogeneity, thereby achieving salient linearity performance. In addition, ParCha utilizes less temperature-sensitive resources but relies more on temperature-invariant modules so that it can be more resilient to temperature fluctuations. A prototype of ParCha is implemented in AMD FPGA XCZU7EV and extensive measurements are conducted. Results demonstrate that the proposed TDC can readily achieve about 30-ps time resolution and a less than 0.3 least significant bit (LSB) integral nonlinearity (INL), even without any calibration efforts. When involving enough resources, the achievable time resolution can be improved to 5 ps, and a less than 0.3 LSB INL is attainable.