An All Digital PLL in 22-nm FD SOI for Hardware Accelerated Embedded Systems

An all-digital phase-locked loop (ADPLL) is designed in 22-nm silicon-on-insulator CMOS. The ADPLL features a digitally control oscillator (DCO) and a phase-frequency detector with a metastability filter. The system achieves power dissipation figures of 3.4 mW at 0.9 V and 0.23 mW at 0.5 V, with a frequency tuning range from 83 MHz to 5.2 GHz, offering wide operating ranges and significant power efficiency. Notably, it consumes only 3.4 mW at 5.2 GHz, exhibits a period jitter of 0.1 ps RMS, and a phase noise of -89 dBc/Hz at a 1 MHz offset frequency. With a compact circuit area of 71 µm by 32 µm, this ADPLL represents a promising advancement in low-power, high-performance clocking solutions.