A 40-ns/100-pF low power full-CMOS 256 K (32 K/spl times/8) SRAM

A fast and low-power full-CMOS 256 K (32 K/spl times/8-b) static RAM is described. Typical access time is 40 ns with a 100-pF load. Power dissipation is 100 mW at 10 MHz and <1 /spl mu/W in standby mode. The low standby power has been achieved by introducing a novel six-transistor, polysilicon-interconnected, double-cross-coupled cell. A novel output buffer design, a data-transition detection (DTD) circuit, and several other circuit techniques are introduced to obtain the speed and low active power dissipation. This chip is made in a 1.3-/spl mu/m, twin-tub, single-poly, double-metal technology with a p epi layer on p/SUP +/ substrate.