Comments on `Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages' [and reply]

For the original article see ibid., vol.SC-21, no.6, p.1120-2 (1986). Recently, S.L. Wong et al, have described a CMOS four-quadrant analog multiplier based on linearized transconductance stages. The commentator points out that the `linearizing' of the Y-input port is unnecessary and does not offer any advantage over using a simple differential pair for the Y-input. The right approach for improving the Y-input dynamic range would be to try to increase the input signal range of the simple differential pair without altering the nature of its transfer characteristics. The original authors disagree, stating that the commenter's point would be valid if the input voltage (V/SUB Y/) range was only restricted by one of the input transistors entering cutoff, but that this is not so. They claim that since the multiplier requires wide X- and Y-input ranges, the use of the linearized Y-cell is necessary.