On the analysis and design of CMOS-bipolar SRAMs

The design and operation of a CMO-bipolar SRAM cell, which incorporates cross-coupled CMOS and n-p-n access transistors, is discussed. A column circuitry to accompany this cell is proposed. Simulation results attributing column access time, standby power dissipation, and active power dissipation of 6-8 ns, 6.5 nW/bit, and 4 mW/b, respectively, for a cell area of ~450 /spl mu/m/SUP 2/, suggest the suitability of this approach for applications requiring density, performance, and moderate power.