A CMOS DRAM controller chip implementation

A DRAM controller which handles up to 128 1-Mb DRAM chips has been developed based on the WE 32100 32-bit microsystem. Fabricated with a 1.5 /spl mu/m twin-tub CMOS technology, nominal DRC devices operate at an internal clock rate of 36 MHz. High circuit speed was achieved by the use of clock-skew minimization techniques to limit clock signal variations to within 3.0 ns throughout the chip, and a modified standard-cell approach called gate-matrix custom cells. The chip implementation process was completed in less than four months and error-free silicon was obtained from the first mask set.