A 2.5-ns, 40-mW, 4/spl times/4 GaAs multiplier in two's complement mode

The design, fabrication, and testing of a very fast GaAs 4/spl times/4 parallel multiplier based on the modified Booth's algorithm are described. The multiplier includes novel transfer logic cells and is the first high-performance GaAs two's-complement multiplier. The circuit, fabricated with 1-/spl mu/m aligned process, exhibits a multiplication time of 2.5 ns (typical 2.7 ns) on the critical path, with a 40-mW power consumption. Per gate the average delay is 120 ps, at 0.2-mW dissipation.