A 256-channel C/SUP 2/MOS LSI time-switch using shift-register pipeline multiplexer

SOS technology has been used to retain the pipeline processing speed advantage by controlling the capacitance of on-chip lines that must be long to provide 256-channel operation. Clocked CMOS (C/SUP 2/MOS) circuits have been used to avoid clock-skew problems. A 1.5-/spl mu/m C/SUP 2/MOS/SOS technology has made it possible to integrate 900 transistors into a 4.0/spl times/2.4-mm/SUP 2/ area, and to realize a 256-channel time-switch LSI, with a 15-ns typical output delay time and a 300-mW power dissipation during 25-MHz operation.