A high-performance custom standard-cell CMOS equalizer for telecommunications applications

A high-performance CMOS programmable amplitude equalizer has been implemented with a dynamic range greater than 100 dB and supply rejection greater than 60 dB at 1 kHz from both supplies. This was accomplished using a balanced architecture. A nonreturn-to-zero sample-and-hold circuit is proposed that is also parasitic-insensitive. The circuits are implemented using a standard-cell methodology.