A single-chip three-level regenerator IC for high-speed optical transmission systems applying duo-binary coding schemes

A three-level regenerator IC operating at 160 Mbit/s or more has been developed for high-speed optical transmission systems, such as local area network and computer links. It was a modified duo-binary class-II coding scheme and provides good performance for long-period pattern transients. Two decision circuits and a nonlinear timing extraction circuit consisting of 430 transistors and resistors are monolithically integrated on a single 2.5/spl times/2.5-mm/SUP 2/ chip using 3-/spl mu/m Si bipolar IC technology. The ICs are primarily designed for a 160-Mbit/s transmission bit rate, with a 1.2-1/24 mark ratio, a 5 V/spl plusmn/10% supply voltage, and 0-70/spl deg/C temperature range. The following characteristics are achieved: 5 mV decision sensitivity, +9.8/-7.8/spl deg/ static pattern jitter, /spl plusmn/7/spl deg/ timing phase shift, transition time of 0.95 ns, and power dissipation of less than 470 mW.