A 4-Kbit associative memory LSI

A 4-Kb (128 words/spl times/32 bits) CMOS associative-memory large-scale integration (LSI) is described. This LSI has all the functions necessary to achieve a self-operative high-speed data search system. Garbage data collection capabilities have been built into the chip in order to develop self-operative systems. The chip's paralleled and pipelined multiple-response resolver makes high-speed, high-throughput data retrieval possible. On-chip extension capabilities for word length and count simplify attainment of a large associative memory system. A newly developed cell circuit allows for simultaneous parallel-writing operation for multiple words. This LSI, which is fabricated using 3-/spl mu/m and double-aluminium-layer CMOS process technology, has a 140-ns measured minimum cycle time and 250-mW measured power dissipation at 5-MHz operation.