Analysis and design optimization of domino CMOS logic with application to standard cells

The application of domino logic to standard-cell-based design is discussed. Domino cells are compatible with static cells and can be used to achieve lower power consumption, as well as a reduction in area or an improvement in system speed. In order to optimise the delay/area performance of domino cells, an analytical model is presented and its validity verified by measurements on test cells implemented in both 5- and 3-/spl mu/m CMOS processes.