Advanced CMOS gate array architecture combining `gate isolation' and programmable routing channels

A description is given of a novel CMOS gate array architecture for LSI/VLSI complexity. The new structure is based on the `gate isolation' technique for logic implementation, in addition to the programmability of the amount of routing channels. This concept uses double-level metal with the first contact level programmable for the circuit customization. The gate array has been designed in a 3-/spl mu/m Si-gate CMOS process. A maximum 2-input gate density of 290 gates/mm/SUP 2/ can be achieved. As a test vehicle for this novel gate array structure, a ninth-order LDI digital filter (4652 transistors) has been designed automatically with the aid of the gate array design system (GARDS) layout tool, on a 3/spl times/3 mm/SUP 2/ gate array size. In a first approach, the filter has been realized with the internal gate structure as used in classical gate arrays, and in a second approach the same filter has been laid out on 60% of the array size using the new concept. In this last version as much as 40% reduction of silicon area has been achieved.