A study on bipolar VLSI gate-arrays assuming four layers of metal

Describes a design study on a bipolar gate-array or masterslice chip with almost 10000 circuits. It assumes 2.5 /spl mu/m groundrules and four layers of metal, i.e. three layers of metal for global wiring and one layer for power and I/O redistribution. It is proven by using actual logic from the IBM 4331 system, that an additional wiring layer increases the circuit density on a masterslice chip by more than a factor of 2. The paper is divided into three sections. Section 1 describes the chip design, the detailed arrangement of internal and external cells with the associated wiring channels and some general aspects of a masterslice design. Section II explains the placement and wiring tools and gives detailed results of a wiring study, comparing a logic design with 2 wiring layers with the same logic implemented with 3 wiring layers (4 layers total). Section III covers the off-chip communication with its associated problems like noise generation by simultaneous driver switching, three-state driver, and embedded RAM macro testing.